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<H2><IMG src="Research Projects_files/think.gif" width=40> Research Projects 
</H2>
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<P><B>Placement Constraints in Floorplan Design </B></P>In floorplan design, it 
is common that a designer will want to control the positions of some modules in 
the final <BR>packing for various purposes like data path alignment, I/O 
connection, etc.. There are several previous works <BR>focusing on a few 
particular kinds of placement constraint. In this project, we study and 
implement the first <BR>``unified method'' to handle all of them simultaneously, 
including pre-placed constraint, range constraint, boundary <BR>constraint, 
alignment, abutment and clustering, etc., in general non-slicing floorplans. We 
have used incremental <BR>updates and an interesting idea of reduced graph to 
improve the runtime of the algorithm.<BR><IMG 
src="Research Projects_files/line.knot.gif"> 
<P><B>Multilevel Interconnect Driven Floorplanning </B></P>In traditional 
floorplanners, area minimization is an important issue. However, due to the 
recent advances in <BR>VLSI technology, the number of transistors in a design 
has been increasing and their switching speeds increasing. <BR>Scalability, 
interconnect delays and routability have become important issues in floorplan 
design. It is necessary to <BR>start interconnect planning and consider 
routability as early as possible. In this project, we study and implement a 
<BR>multilevel interconnect driven floorplanner. In the multilevel approach, the 
floorplanning procedure will be divided <BR>into two phases: the clustering 
phase and the refinement phase, and a floorplan solution will be evaluated by 
its <BR>area, wirelength, congestion and routability. In the calculation of the 
congestion information, constraints on buffer <BR>insertion will also be 
considered.<BR><IMG src="Research Projects_files/line.knot.gif"> 
<P><B>Module Sizing and Shaping in Floorplan Design </B></P>In the early stage 
of floorplan design, many modules have large flexibilities in shape (soft 
modules). Handling soft <BR>modules in general non-slicing floorplan is a 
complicated problem. In this project, we solved this problem optimally <BR>by 
geometric programming using the Lagrangian relaxation technique. The resulting 
Lagrangian relaxation subproblem <BR>is so simple that the optimal size of each 
module can be computed in linear time. We implemented this method in a 
<BR>simulated annealing framework based on the sequence pair representation. The 
geometric program is invoked in every <BR>iteration of the annealing process to 
compute the optimal size of each module to give the best packing. Our technique 
<BR>will also be applicable to other floorplanning algorithms which use 
constraint graphs to find module positions in the <BR>final packing.<BR><IMG 
src="Research Projects_files/line.knot.gif"> 
<P><B>Floorplan Representation </B></P>
<P>... Under construction </P><IMG src="Research Projects_files/line.knot.gif"> 
<P><B>Technology Mapping for Time Multiplexed FPGA </B></P>
<P>... Under construction </P><IMG src="Research Projects_files/line.knot.gif"> 
<P><B>Interconnect-Driven Floorplanning - Congestion Estimation and Buffer 
Planning </B></P>
<P>... Under construction </P><IMG src="Research Projects_files/line.knot.gif"> 
<P><B>Circuit Partitioning </B></P>
<P>... Under construction </P><IMG src="Research Projects_files/line.knot.gif"> 
<P><B>Circuit Retiming with Interconnect Delay </B></P>
<P>... Under construction </P></BODY></HTML>
